As is well known, the current strive to provide non-volatile memories of enhanced capacity brings about a problem of time necessary for testing the memories. Many of the operations for testing a memory that is comprised essentially of a matrix of memory cells involve scanning the whole matrix serially.
Testing the whole memory matrix is necessary, in particular, to find out potentially damaged memory locations and substitute them with redundant memory locations in order that the memory can be restored to full performance.
Consequently, the test step requires that a number of readings from each location in the memory matrix and a comparison of the result of each reading with a set of reference values, generally a predetermined pattern, be performed.
As a damaged memory location is detected, meaning that the value read from the memory location and the pattern value fail to match with each other, it is common practice to completely substitute a redundant column for the column that contains the faulty location.
The device employed to perform this comparison, hence the test, is known as the testing machine.
All the testing steps are currently timed by the testing machine and are carried out at slower rates than the memory device read rate in normal operation. The testing machine, in addition to supplying the signals that activate the read operations during the test, stores the results in an internal memory of its own, and then compares such results with a pattern stored in the machine in order to check for the presence of errors.
It can be appreciated, therefore, that the testing procedure and all the operations involved, generally referred to as the testing operations hereinafter, are dependent on the timing of the testing machine rather than the normally higher internal rates of the memory device.
It is to be noted that the testing machine timing is made longer by the presence of parasitic elements outside the memory device under test, specifically, parasitic elements residing in the hardware of the testing machine. These parasitic elements are present during tests that are carried out during the manufacturing process of the semiconductor wafer containing the memory device to be tested.
Also, the read parallelism compatible with the testing machine is limited by the number of outputs provided in the memory device being tested, rather than by the actual number of readings that can be effected simultaneously by the internal circuitry of the memory device.
U.S. Pat. No. 6,085,334 to Giles et al. discloses a method of testing and repairing an integrated memory, whereby faults induced by environmental conditions can be detected, the memory test being repeated under different conditions of operation. In particular, the Giles et al. method includes generating signals that are indicative of an error state of the memory under first and second conditions of operation, disagreement of the signals allowing faults due to environmental conditions to be detected.
The above-referenced document also discloses autotesting and autorepairing circuits that are incorporated in the semiconductor device where the memory is integrated and adapted to implement the claimed method.
An underlying technical problem solved by this invention is to provide an autotesting method of a matrix of memory cells and a corresponding memory device having a autotesting architecture, whereby the time required to complete the testing operations on the memory device can be reduced dramatically and the limitations with which prior testing machines and procedures are beset are overcome.